1. Field of the Invention
This invention relates to Read Only Memory (ROM) integrated circuit devices, and more particularly to improved structural arrangements thereof, and to methods of manufacture thereof.
2. Description of Related Art
ROM devices are standard components of modern computer systems. A MOSFET ROM comprises an array of Metal Oxide Semiconductor Field Effect Transistor (MOSFET's) arranged in columns and rows, wherein predetermined MOSFET's are either permanently conductive or nonconductive as a function of the variety of transistor. The alternative on/off operation with changes in the states of operation of the MOSFETs is adapted to use for storage of data, which remains in the device when the external power supply is off.
A ROM device includes an array of parallel, closely spaced lines regions formed of a heavily doped impurity in a semiconductor substrate having an opposite type of back-ground impurity. An insulating layer is formed on the surface of the substrate. Another array of closely spaced conductive lines formed on the surface of the insulating layer is arranged at right angles to the spaced lines in the substrate. Insulating layers are formed on the upper array of conductive lines. A metallurgy layer connects the two arrays of lines to circuits to address the lines and to read the data stored in the ROM, as is well known in the art.
At the intersection of a conductive line in the upper array which is commonly referred to in most cases as a "wordline" and a pair of adjacent lines in the substrate, known in most cases as the "bitlines", a MOSFET is formed. The spaced lines in the substrate comprise the source and drain of the MOSFET. The conductive wordline serves as the gate electrode of the MOSFET. Certain predetermined MOSFET's are made permanently non-conductive (turned off).
A problem with the trend in the semiconductor industry is the ever increasing density of circuits on a device. Accordingly, an object of this invention is to provide an improved design for a very high density ROM device.
Another objective, always desirable in electronic devices and other technologies, is the simplification of the structure and operation of devices. In the case of the very large number of circuits in the state of the art ROMs the need for simplification of structure and operation is as desirable as ever. Accordingly, it is an important object of this invention is to provide for simplification of the structure and the operation of ROM devices.
More recently a Thin Film Transistor (TFT) ROM device design has been described in U.S. Pat. Nos. 5,358,887 and 5,383,149 of Hong for "ULSI Mask ROM Structure and Method of Manufacture" which is formed above an oxide layer on top of a silicon substrate providing a double density memory array. The wordline array is composed of transversely disposed conductors sandwiched between two arrays of bitlines which are orthogonally disposed relative to the wordline array. The two arrays of bitlines are stacked with one above and with one below the wordline array. A first gate oxide layer is located between the wordline array and a first one of the array of bitlines and a second gate oxide layer is located between the wordline array and the other of the arrays of bitlines. The two parallel sets of polysilicon thin film transistors are formed with the wordlines serving as gates for the transistors.
An alternative ROM device provides a double density memory array in which a wordline array is composed of transversely disposed conductors. The wordline array is sandwiched between two bitlines arrays disposed orthogonally relative to the wordline array with bitlines arrays stacked with one above and with one below the wordline array. A first gate oxide layer is located between the wordline array and a first one of the arrays of bitlines. A second gate oxide layer is located between the wordline array and the other array of bitlines. Two parallel sets of polysilicon thin film transistors are formed with the wordlines serving as gates for the transistors.
Further progress is required in ROM design and construction to further increase the density of storage capacity beyond what has been provided by the MOSFET and TFT designs described above.